High density single transistor ferroelectric non-volatile memory

ABSTRACT

A single transistor ferroelectric memory (“FEM”) cell, useful for high density ferroelectric random access memory (“FRAM”) applications, and a method for making the same, are herein disclosed. The FEM cell comprises a FEM gate unit having a top electrode, a ferroelectric material layer, and a bottom electrode. The FEM gate unit is disposed above a semiconductor substrate having defined on it a well region and channel of a first conductive type and a source and drain of a second conductive type. A conductive upper polysilicon layer covers both the FEM gate unit and a portion of the source region and is in electrical communication with the top electrode of the FEM gate unit. The drain is in electrical communication with the bottom electrode of the FEM gate unit and serves as the bit line for the FEM memory cell. The source is shared between the present memory cell and an adjacent cell.

BACKGROUND OF THE INVENTION

[0001] 1. The Field of the Invention

[0002] The present invention relates to non-volatile memory cells. Moreparticularly, the present invention relates to an apparatus and methodfor providing high-density single transistor memory cells for use insemiconductor devices.

[0003] 2. The Relevant Technology

[0004] It is well known that ferroelectric materials may be used tostore information in a non-volatile memory cell. Ferroelectric materialspossess two characteristics that make them ideal for such use: abi-stable polarization (positive or negative) that corresponds to a “1”or a “0” digital logic state, and the ability to retain such states inthe absence of electrical power to the memory cell. The polarizationeffect demonstrated by ferroelectric materials is best understood as anon-zero charge per unit area on the ferroelectric device (such as acapacitor) that exists at zero voltage.

[0005] A variety of ferroelectric memory (“FEM”) structures are known inthe art, including ferroelectric random access memories (“FRAMs”) thatemploy two transistor-two capacitor (2T/2C) and one transistor-onecapacitor (1T/1C) FEM cells on integrated circuit chips. In such FEMcells, the capacitor is generally made by sandwiching a thinferroelectric film between two electrically conductive electrodes. Alsoknown in the art is the use of a ferroelectric film to form a fieldeffect transistor (“FET”), where the gate of the FET includes aferroelectric material. A popular type of such ferroelectricgate-controlled devices is the metal-ferroelectric-metal-oxide-silicon(“MFMOS”) FET, often incorporated in FRAMs. FRAMs having MFMOS FETstructures are often desired over the transistor-capacitorconfigurations because they occupy less area on the semiconductorsurface, and because they provide non-destructive readout (“NDRO”) ofthe FRAM cells. With the ever-present drive for circuit size reductionin integrated circuit chip fabrication, however, attention is directedto creating smaller, more compact FEM cells. A need therefore exists toproduce a MFMOS FRAM cell that may be incorporated into a high densitymemory cell array while, at the same time, preserving FRAM circuitdesigns.

SUMMARY OF THE INVENTION

[0006] It is therefore an object of the present invention to provide anon-volatile FEM cell with nondestructive readout characteristics foruse in high density FRAM cell arrays. Briefly summarized, embodiments ofthe present invention are directed to a FEM cell suitable for use inhigh-density memory cell arrays, and a method for making such cells.Each FEM cell comprises a single transistor having a gate unitcomprising a ferroelectric thin film deposited between a top and bottomelectrode. The ferroelectric gate unit resides atop a semiconductorsubstrate having defined on it doped regions of a first and secondconductive type that define a well and channel region, and source/drainregions, respectively. A gate oxide and a lower polysilicon layer aredisposed between the ferroelectric gate unit and semiconductorsubstrate. An upper polysilicon layer covers the ferroelectric gate unitand electrically connects it with the source region on the semiconductorsubstrate. The sides of the ferroelectric gate unit are sealed with anappropriate sealant, such as Si₃N₄, to prevent damage to theferroelectric material, during chip fabrication.

[0007] The FEM cell of the present invention is preferably integrated ina memory cell array on a integrated circuit chip with the array havinghorizontal rows and vertical columns of memory cells. Each FEM cellwithin such a memory array includes a drain, channel, and ferroelectricgate unit, but the source is shared between the present FEM cell and anadjacent cell. In this way, a higher density of FEM cells may beconfigured within the memory cell array.

[0008] In operation, each FEM cell of a memory array is electricallyconnected to a bit line, source line, and word line. The drain region ofthe FEM cell comprises the bit line, the upper polysilicon layercomprises the word line, and the shared source region defines the sourceline. In this manner, the top and bottom electrodes of the ferroelectricgate unit are electrically coupled to the word line and bit line,respectively. These electrical couplings enable the ferroelectricmaterial between the top and bottom electrodes to be polarized inconnection with program and erase operations. Through such program anderase operations, the ferroelectric material is polarized into one ofits bi-stable orientations corresponding to a “1” or “0” digital logic.The logic state is maintained by the ferroelectric material after theprogram or erase operation is completed and electrical power is removedfrom the FEM cell. A subsequent read operation senses the logic state ofthe ferroelectric material via accompanying circuitry. Thus the FEM cellmemory is stored in a non-volatile manner to be subsequently readwithout disturbing the logic state of the cell. Memory cell densities of16 megabits (“Mbits”) and above are possible with the present invention.

[0009] These and other objects and features of the present inventionwill become more fully apparent from the following description andappended claims, or may be learned by the practice of the invention asset forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order that the manner in which the above recited and otheradvantages and features of the invention are obtained, a more particulardescription of the invention briefly described above will be rendered byreference to specific embodiments thereof that are illustrated in theappended drawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be consideredlimiting of its scope, the invention will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings in which:

[0011]FIG. 1 is a cross sectional side view of a semiconductor substrateupon which a single-transistor ferroelectric memory cell is constructedaccording to the present invention;

[0012]FIG. 2 is a cross sectional side view of a step in theconstruction of the FEM cell;

[0013]FIG. 3 is a cross sectional side view of a further step in theconstruction of the FEM cell;

[0014]FIG. 4 is a cross sectional side view of a further step in theconstruction of the FEM cell;

[0015]FIG. 5 is a cross sectional side view of two FEM cells constructedaccording to the present invention;

[0016]FIG. 6 is a representative top view of various FEM cells disposedin a memory cell array in accordance with the present invention;

[0017]FIG. 7 is an electrical diagram depicting the circuitry of a FEMcell within a memory cell array.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] A ferroelectric memory (“FEM”) cell of the present invention isconstructed in the manner described below. Referring to FIG. 1, asemiconductor substrate 10 is shown upon which a FEM cell is fabricated.Preferably, the substrate 10 comprises silicon, though other suitablesubstrates may also be used. A p-well layer 12 is formed in thesubstrate 10, and is also referred to herein as a region of a firstconductive type. The p-well 12 is preferably formed by boron or boroncompound ion implantation and diffusion techniques well known in theart, but other suitable substances may be employed as well to form thep-well. Alternatively, other techniques, such as plasma immersion ionimplantation, gas immersion laser doping, or plasma assisted doping, maybe used to dope this and other doped structures in the FEM cell. The ionimplantation is, for example, conducted at an energy of 50 KeV and at adosage of 8×10¹² cm⁻². The p-well 12 is isolated from other areas of thesubstrate 10 preferably by a shallow trench isolation process, thusforming isolation trenches 14. Other isolation methods may be employedto isolate the substrate 10 including, for example, field oxideapplication.

[0019] Referring now to FIG. 2, three shallow n-type regions, alsoreferred to herein as regions of a second conductive type and comprisinga source region 16 and two drain regions 18, are implanted on the p-well12 preferably by ion implantation and diffusion. Preferably, arsenic isemployed as the dopant at an energy of about 70 KeV and a dosage ofabout 3×10¹⁵ cm², though again it is appreciated that other appropriatedopants could be utilized including, for example, phosphorus. Each drainregion 18 is oppositely disposed on either side of the source region 16,with each drain region preferably having a spacing from the sourceregion of about 0.18 to 0.35 μm. A channel 19 comprises the shallowportion of the p-well 12 that resides in the spacing between the source16 and each drain 18. The p-well 12, source and drain regions 16 and 18,and the channel 19 are diffused to provide the proper electricalcharacteristics to such regions. A gate oxide layer 20, preferably SiO₂,is grown over the source 16, drains 18, and p-well 12 using knownprocesses, including thermal oxidation or chemical vapor deposition(“CVD”).

[0020]FIG. 3 depicts the next step in the FEM cell construction, thatbeing the deposition of a lower polycrystalline silicon (“polysilicon”)layer 22 over the gate oxide 20. After being deposited to a preferredthickness of about 500 to 700 Å, the lower polysilicon layer 22 is dopedto the desired polarity, which preferably is n-type. The lowerpolysilicon layer 22 assists in protecting the gate oxide 20 from damageduring further process steps.

[0021] Formation of a FEM gate unit is begun atop the polysilicon layer22 by depositing a bottom electrode 26. The bottom electrode 26 isdeposited by known deposition processes, such as physical vapordeposition (“PVD”) or chemical vapor deposition (“CVD”), and preferablycomprises platinum. Alternatively, other materials that may be used toform the bottom electrode 26 include ruthenium, iridium, RuO, or IrO₂,or other suitable noble metal oxides or alloys thereof. The thickness ofthe electrode 26 is from about 500 to 1,500 Å. It is noted that, in analternative embodiment, the lower polysilicon layer 22 may be eliminatedfrom the FEM cell. In such an embodiment, the bottom electrode 26 wouldprovide the protective function for the gate oxide 20 formerly providedby the lower polysilicon layer 22 as noted above.

[0022] Next, a ferroelectric material layer 28 is deposited on thebottom electrode 26 using known techniques such as CVD, sputtering, andsol-gel processing. Preferably, the ferroelectric material 28 comprisesPb(Zr, Ti)O₃, known as lead zirconate titanate oxide (“PZT”), and isdeposited to a thickness from about 800 to 2,000 Å. Alternativeferroelectric materials that may also be used include SrBiTa₂O₉, knownas strontium bismuth tantalite oxide (“SBT”), Pb₅Ge₃O₁₁, and BaTiO₃.

[0023] A top electrode 30 is then formed over the ferroelectric material28 to a thickness of from about 500 to 1,500 Å. As with the bottomelectrode 26, the top electrode 30 is deposited by known depositionprocesses, such as PVD or CVD, and preferably comprises platinum.Alternatively, other materials that may be used to form the topelectrode 30 include ruthenium, iridium, RuO, or IrO₂, or other suitablenoble metal oxides or alloys thereof.

[0024] At this point the top electrode 30, ferroelectric material 28,bottom electrode 26, and lower polysilicon layer 22 are cut and sized byetching or similar techniques above the source 16 such that two FEM gateunits 32 are formed thereby as shown in FIG. 4. Each FEM gate unit 32 isdisposed above a respective drain 18 and a portion of the p-well 12defined in the semiconductor substrate 10. Each of the two FEM gateunits 32 are disposed partially over the source 16. A sealing layer 34is applied to the sides of each FEM cell 32 to protect the ferroelectricmaterial 28 from hydrogen damage during further fabrication processsteps. The sealing layer is preferably deposited by CVD and comprises ofSi₃N₄, though Al₂O₃ or similar substances may also be employed asappreciated by one of skill in the art. It is noted here that thevarious layers of the FEM gate unit 32 need not precisely resemble theconfiguration as shown, as their shapes may be modified by variousfabrication process steps. For the sake of clarity, however, the FEMgate unit 32 is depicted having aligned and contiguous side walls.

[0025] Referring now to FIG. 5, an upper polysilicon layer 36 is showndeposited atop both FEM gate units 32, isolation trenches 14, and theregion above the source 16. The upper polysilicon layer is preferablyapproximately 800 to 1,500 Å in thickness and appropriately doped so asto be electrically conductive. Such doping may be provided by doping Asor P during the CVD polysilicon process. At this point furthercomplimentary metal-oxide-semiconductor (“CMOS”) fabrication processsteps may be performed as is known in the art, including metallizationsteps that connect conductive electrodes (not shown) to the source 16,the drain 18, and the upper polysilicon layer 36. Two FEM cells 50 asdescribed above are therefore depicted in FIG. 5.

[0026]FIG. 6 is a top view of various components of several FEM cells 50arranged in a memory cell array. The figure depicts the source 16 andthe drains 18 as doped regions extending in a columnar fashion along thesemiconductor substrate 10 and upper polysilicon layers 36 partiallyshown extending laterally along the top portion of the various cells.Other components of the FEM cell 50 have been omitted from the figurefor clarity. In the FEM cell 50 of the present invention, the source 16serves as the source line to the cell, while the drain 18 serves as thebit line and the upper polysilicon layer 36 serves as the word line. Theword line (upper polysilicon layer) is in electrical communication withthe top electrode 30 of the FEM gate unit 32, while the bit line (drain)overlaps the bottom electrode 26 through a coupling region 52, whichresides directly above the drain 18 as outlined in FIGS. 5 and 6. Thiselectrical scheme is referred to herein as drain-side coupling and itcomprises a means for controlling the polarization of the ferroelectricmaterial. In this way, the FEM cell 50 is programmed andnon-destructively read, as described below.

[0027]FIG. 7 is an electrical diagram of one of the two FEM cells 50 ofFIG. 5. The FEM cell 50 disclosed herein represents a ferroelectricgate, single-transistor MFMOS transistor. The FEM cell 50, formedaccording to the present invention, is an efficient non-volatile storagedevice because the FEM gate unit 32, disposed above the channel 19, isable to shift the polarity of the channel, thus reducing the thresholdvoltage, i.e., the voltage potential that needs to exist between thesource 16 and the drain 18 in order for an electrical current to beproduced. A low threshold voltage allows current to more easily flowfrom the source 16 to the drain 18 via the channel 19. Conversely, theFEM gate unit 32 may shift the polarity of the channel 19, therebyincreasing the threshold voltage of the channel and restricting currentflow from the source 16 to the drain 18.

[0028] To program a single FEM cell 50 to a “1” digital logic (the highthreshold state), a positive voltage of from about 3 to 8 V is appliedto the bottom electrode 26 via the bit line (drain 18), while the topelectrode 30 is grounded via the word line (upper polysilicon layer 36).The voltage potential thus created is in amount greater than thecoercive voltage, which is the voltage necessary to change thepolarization state of the ferroelectric material 28. This causes theferroelectric material 28 to polarize in an upward (or positive)direction. Once the voltage potential is removed, the ferroelectricmaterial 28 substantially maintains the voltage-induced positivepolarization, and now resides in one of its bi-stable polarizationstates where a small amount of positive charge is located at theinterface of the ferroelectric material 28 and the top electrode 30, anda small amount of negative charge is located at the interface of theferroelectric material 28 and the bottom electrode 26. This negativecharge at the bottom interface in turn induces a small positive chargebuild-up in the channel 19, thus increasing the threshold voltagebetween the source 16 and the drain 18.

[0029] To program (or erase) the FEM cell 50 to a “0” digital logic (thelow threshold state), a positive voltage of from about 3 to 8 V isapplied to the top electrode via the word line, while the bottomelectrode 26 is grounded via the bit line. Now the ferroelectricmaterial 28 polarizes in a downward (or negative) direction. Once thevoltage potential is removed, the ferroelectric material 28 remains inits other bi-stable polarization state, and in a similar manner to thedescription above, induces a small negative charge build-up in thechannel 19, thus decreasing the threshold voltage between the source 16and the drain 18.

[0030] To read the programmed FEM cell 50, a positive voltage of fromabout 3 to 8 V is applied to both the word line and the bit line, whilethe source line is grounded. Sense circuitry incorporated into thememory cell array then detects the amount of current flowing from thedrain 18 to the source 16 across channel 19, which current is determinedby the polarization-dependent threshold voltage induced by theprogrammed ferroelectric material. The sense circuitry thus determineswhether the FEM cell 50 is holding a “1” or a “0” digital logic, andthis information is then forwarded to be processed as needed by otherelectronic circuitry. It is noted that the information held by the FEMcell 50 is not destroyed during the read process, thus advantageouslyeliminating the need to re-program the cell after it has been read. Thispreserves the longevity of the ferroelectric material 28, which issubject to fatigue as the number of switching operations increases.

[0031] It should be appreciated that the FEM cell fabrication methoddisclosed herein comprises a part of a complete integrated circuitfabrication process for forming non-volatile memory or similar devices.It is understood that the FEM cell and method for making the same may beapplicable to other semiconductor technologies where ferroelectricmaterials are employed.

[0032] In summary, the FEM cell disclosed herein enables highly compactmemory cell arrays by utilizing both drain side electrical coupling ofthe drain and FEM gate unit and memory cell source line sharing. FRAMshaving a memory density exceeding 16 Mbits are possible using this FEMcell. Moreover, the FEM cell is fabricated using procedures known in theart. Because the reading of the present FEM cell is non-destructive, nore-writing of cell is necessary after a read operation is performed, andthe operating lifetime of the ferroelectric material is prolonged. TheFEM cell of the present invention may be the primary component of amemory cell as described herein, or it may be coupled to othertransistors by conventional means that are well known to one of skill inthe art.

[0033] The present claimed invention may be embodied in other specificforms without departing from its spirit or essential characteristics.The described embodiments are to be considered in all respects only asillustrative, not restrictive. The scope of the invention is, therefore,indicated by the appended claims rather than by the foregoingdescription. All changes that come within the meaning and range ofequivalency of the claims are to be embraced within their scope.

What is claimed and desired to be secured by United States LettersPatent is:
 1. A single transistor ferroelectric memory cell, comprising:a semiconductor substrate having defined thereon: a first conductiveregion of a first conductive type; a source region of a secondconductive type defined in said first conductive region, said sourceregion sized and configured to comprise a portion of the ferroelectricmemory cell and an adjacent ferroelectric memory cell; and a drainregion also of a second conductive type defined in said first conductiveregion, said drain region being spaced apart from said source regionsuch that a channel region comprising a portion of said first conductiveregion is defined between said source region and said drain region; agate oxide layer disposed on said semiconductor substrate to cover saiddrain, channel, and source regions; a ferroelectric gate unit disposedon said gate oxide layer comprising: a bottom electrode in electricalcommunication with said drain region; a top electrode; a ferroelectriclayer disposed between said bottom and said top electrode; and a sealinglayer disposed on each side of said ferroelectric gate unit; and anupper conductive layer disposed on said ferroelectric gate unit and aportion of said gate oxide coating such that said upper conductive layerand said top electrode of said ferroelectric gate unit are in electricalcommunication.
 2. A single transistor ferroelectric memory cell asdefined in claim 1, wherein said upper conductive layer comprisespolysilicon doped to a conductive state.
 3. A single transistorferroelectric memory cell as defined in claim 1, further comprising aplurality of shallow isolation trenches defined in the semiconductorsubstrate.
 4. A single transistor ferroelectric memory cell as definedin claim 1, further comprising a lower polysilicon layer disposedbetween said gate oxide layer and said bottom electrode, the lowerpolysilicon layer doped to a conductive state and having a thickness athickness of from about 500 to 700 Å.
 5. A single transistorferroelectric memory cell as defined in claim 1, wherein said firstconductive region of a first conductive type includes ions implantedtherein, said ions taken from the group consisting of B and BF₂.
 6. Asingle transistor ferroelectric memory cell as defined in claim 1,wherein said source and drain regions of a second conductive typeinclude ions implanted therein, said ions taken from the groupconsisting of P and As.
 7. A single transistor ferroelectric memory cellas defined in claim 1, wherein said bottom and top electrode arecomposed of material taken from the group consisting of Pt, Ir, IrO₂,Ru, and RuO, said bottom and top electrode each having a thickness ofabout 500 to 1,500 Å.
 8. A single transistor ferroelectric memory cellas defined in claim 1, wherein said ferroelectric layer is comprised ofmaterial taken from the group consisting of Pb(Zr, Ti)O₃, SrBiTa₂O₉,Pb₅Ge₃O₁₁, and BaTiO₃, said ferroelectric layer having a thickness ofabout 800 to 2,000 Å.
 9. A single transistor ferroelectric memory cellas defined in claim 1, wherein said sealing layer comprises materialtaken from the group consisting of Si₃N₄ and Al₂O₃.
 10. A singletransistor ferroelectric memory cell as defined in claim 1, wherein thespacing between said source region and said drain region isapproximately 0.18 to 0.35 μm.
 11. A method for forming a singletransistor ferroelectric memory cell, the method comprising the stepsof: providing a semiconductor substrate; implanting ions in saidsemiconductor substrate to form a first conductive region of a firstconductive type; implanting ions in said first conductive region to forma source region of a second conductive type and a drain region also of asecond conductive type, said source region being spaced apart from saiddrain region such that a channel portion of said first conductive regionresides between said source region and said drain region, said sourceregion also disposed such that it comprises a portion of the presentferroelectric memory cell and a portion of an adjacent ferroelectricmemory cell; disposing on said channel region, drain region, and atleast a portion of said source region a gate oxide layer; disposing onsaid gate oxide layer a ferroelectric gate unit such that said drainregion, said channel region, and at least a portion of said sourceregion are covered thereby, the ferroelectric gate unit comprising: abottom electrode, said bottom electrode sized and configured to be inelectrical communication with said drain region, the drain region alsocomprising the bit line for the memory cell; a ferroelectric layer; anda top electrode; coating said ferroelectric gate unit and at least aportion of said source region with an upper polysilicon layer such thatsaid top electrode of said ferroelectric gate unit is in electricalcommunication with said upper polysilicon layer; and doping said upperpolysilicon layer to a conductive state.
 12. A method for forming asingle transistor ferroelectric memory cell as defined in claim 11,further comprising the step of forming on the structure resulting fromthe previous step a source electrode, a drain electrode and an upperpolysilicon layer electrode.
 13. A method for forming a singletransistor ferroelectric memory cell as defined in claim 12, furthercomprising the step of: forming a lower polysilicon layer over said gateoxide layer and beneath said ferroelectric gate unit, the lowerpolysilicon layer having a thickness of from about 500 to 700 Å;
 14. Amethod for forming a single transistor ferroelectric memory cell asdefined in claim 13, further comprising the step of: doping said lowerpolysilicon layer to a conductive state.
 15. A method for forming asingle transistor ferroelectric memory cell as defined in claim 14,further comprising the step of: isolating the ferroelectric memory cellby defining shallow trenches in the semiconductor substrate.
 16. Amethod for forming a single transistor ferroelectric memory cell asdefined in claim 15, further comprising the step of: depositing asealing layer on each side of said ferroelectric gate unit, said sealinglayer comprising material taken from the group consisting of Si₃N₄ andAl₂O₃.
 17. A method for forming a single transistor ferroelectric memorycell as defined in claim 16, wherein the gate oxide layer comprisesSiO₂.
 18. A method for forming a single transistor ferroelectric memorycell as defined in claim 17, wherein the implanting ions in saidsemiconductor substrate to form a first conductive region step includesimplanting a dopant for taken from the group consisting of B or BF₂. 19.A method for forming a single transistor ferroelectric memory cell asdefined in claim 18, wherein the implanting ions in said firstconductive region step includes implanting a dopant for source and drainregions of second conductive type taken from the group consisting of Pand As.
 20. A method for forming a single transistor ferroelectricmemory cell as defined in claim 19, wherein said bottom and topelectrode are composed of material taken from the group consisting ofPt, Ir, IrO₂, Ru, and RuO, said bottom and top electrode each having athickness of about 500 to 1,500 Å.
 21. A method for forming a singletransistor ferroelectric memory cell as defined in claim 20, whereinsaid ferroelectric layer is comprised of material taken from the groupconsisting of Pb(Zr, Ti)O₃, SrBiTa₂O₉, Pb₅Ge₃O_(11,) and BaTiO₃, saidferroelectric layer having a thickness of about 800 to 2,000 Å.
 22. Aferroelectric memory cell comprising: a ferroelectric gate unitcomprising a top electrode, a layer of ferroelectric material, and abottom electrode; a semiconductor substrate having: a drain; a source; achannel; a gate oxide; and means for controlling the polarization ofsaid layer of ferroelectric material.
 23. A ferroelectric memory cell asdefined in claim 22, wherein the means for controlling the polarizationof said layer of ferroelectric material comprises an electricalconnection between said drain and said bottom electrode of saidferroelectric gate unit.
 24. A ferroelectric memory cell as defined inclaim 23, wherein the means for controlling the polarization of saidlayer of ferroelectric material further comprises an upper polysiliconlayer deposited on top of said ferroelectric gate unit such thatelectrical communication is established between said top electrode andsaid conducting polysilicon layer.
 25. A ferroelectric memory cell asdefined in claim 22, further comprising a lower polysilicon layerdeposited between the ferroelectric gate unit and the gate oxide.
 26. Amethod for programming a ferroelectric memory cell having aferroelectric gate unit comprising a top electrode, a ferroelectriclayer, and a bottom electrode, the memory cell also having asemiconductor substrate comprising a source region and drain region of afirst conductive type, the source region configured to comprise aportion of the present ferroelectric memory cell and an adjacentferroelectric memory cell, and a channel between said source region anddrain region of a second conductive type, a gate oxide layer beingdisposed between said semiconductor substrate and said ferroelectricgate unit, and a conductive top layer disposed on said ferroelectricgate unit and at least a portion of said source region, the methodcomprising the steps of: applying a positive voltage to the drainregion, thereby charging the bottom electrode of the ferroelectric gateunit; and grounding the conductive top layer, thereby grounding the topelectrode of the ferroelectric gate unit and polarizing theferroelectric layer of the ferroelectric gate unit to a programmedpolarization.
 27. A method for programming a ferroelectric memory cellas defined in claim 26, wherein the positive voltage applied to thedrain region is in the range of about 3 to 8 V.
 28. A method for erasinga ferroelectric memory cell having a ferroelectric gate unit comprisinga top electrode, a ferroelectric layer, and a bottom electrode, thememory cell also having a semiconductor substrate comprising a sourceregion and drain region of a first conductive type, the source regionconfigured to comprise a portion of the present ferroelectric memorycell and an adjacent ferroelectric memory cell, and a channel betweensaid source region and drain region of a second conductive type, a gateoxide layer being disposed between said semiconductor substrate and saidferroelectric gate unit, and a conductive top layer disposed on saidferroelectric gate unit and at least a portion of said source region,the method comprising the steps of: applying a positive voltage to theconductive top layer, thereby charging the top electrode of theferroelectric gate unit; and grounding the drain region such that theferroelectric layer of the ferroelectric gate unit is polarized to anerased polarization.
 29. A method for programming a ferroelectric memorycell as defined in claim 28, wherein the positive voltage applied to theconductive layer is in the range of about 3 to 8 V.
 30. A method forreading a ferroelectric memory cell having a ferroelectric gate unitcomprising a top electrode, a ferroelectric layer, and a bottomelectrode, the memory cell also having a semiconductor substratecomprising a source region and drain region of a first conductive type,the source region configured to comprise a portion of the presentferroelectric memory cell and an adjacent ferroelectric memory cell, anda channel between said source region and drain region of a secondconductive type, a gate oxide layer being disposed between saidsemiconductor substrate and said ferroelectric gate unit, and aconductive top layer disposed on said ferroelectric gate unit and atleast a portion of said source region, the method comprising the stepsof: applying a positive voltage to the conductive top layer; applying apositive voltage to the drain region; grounding the source region; andproviding sensing circuitry electrically connected to the ferroelectricmemory cell to enable reading of the resulting level of current passingthrough the channel region.
 31. A method for programming a ferroelectricmemory cell as defined in claim 30, wherein the positive voltage appliedto the conductive top layer and the drain region is in the range ofabout 3 to 8 V.